Following the shipment of the first EUV DRAM in March last year, increasing the number of EUV layers to five layers at this stage will provide a better solution for DDR5.
Jooyoung Lee, senior vice president and head of DRAM products and technology at Samsung Electronics, said: “By pioneering key patterning innovations, we have been leading the DRAM market for nearly three years. Today, Samsung is building a multi-layer EUV Another technological milestone, this technology has achieved the extremes of 14 nanometers-this is a feat that cannot be achieved by the traditional ArF process. On this basis, we will continue to make changes in 5G, AI, and the virtual world. High-performance and larger-capacity data-driven computing provide the most differentiated memory solutions.”
Samsung has achieved ultra-high bit density by adding five EUV layers to 14nm DRAM while increasing the overall wafer productivity by approximately 20%. In addition, compared with the previous generation of DRAM, the 14-nanometer process helps reduce power consumption by nearly 20%.
According to the latest DDR5 standard, Samsung’s 14-nanometer DRAM can bring an ultra-high speed of 7.2Gbps, which is more than twice the highest speed of 3.2Gbps of the previous generation DDR4.
The DNS understands that at the same time Samsung plans to expand its 14-nanometer DDR5 product portfolio to support data center, supercomputer and enterprise server applications. In addition, Samsung expects to increase its 14-nanometer DRAM chip density to 24Gb to better meet the rapidly growing data needs of global IT systems.